This application is based upon and claims the benefit of priority from prior Japanese Patent Application P2002-87509 filed on Mar. 27, 2002; the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a microwave integrated circuit, more specifically, to a structure of a microwave integrated circuit using a chip element.
2. Description of the Related Art
Along with utilization of quasi-millimeter-wave and millimeter-wave bands in recent years, a microwave integrated circuit which can operate efficiently in these bands has been in demand.
A mounting structure of an earlier microwave semiconductor device inside a microwave integrated circuit will be described by use of FIG. 1. FIG. 1 is a view showing an example of a microwave detection circuit in which a detector diode is used as a semiconductor chip 101 and the detector diode is bonded to a microwave transmission line such as a microstrip line.
A lower electrode 103 of a semiconductor chip 101 is soldered to a mount pad 116 with a gold-tin solder or the like. The mount pad 116 is connected to a ground plate 118b of a microstrip line formed on a rear surface of a dielectric substrate 115 through a via hole (not shown) and is thereby grounded. An upper electrode 102 of the semiconductor chip 101 is bonded to a point C on a signal line 118a of a microstrip line formed on a front surface of the dielectric substrate 115, with a bonding wire 111 such as a gold wire. Moreover, in order to provide the semiconductor chip 101 with a direct-current bias, a direct-current bias circuit unit 119 and the signal line 118a are bonded together through a relay bonding pad 117 with bonding wires 111, such as gold wires, having a sufficiently large inductance.
In the detection circuit, a microwave signal is inputted from the signal line 118a, and a detection output is obtained at the direct-current bias circuit section 119. Firstly, an input signal is propagated on the impedance-matched signal line 118a. However, an impedance mismatch occurs at the point C, which is a bonding point to the semiconductor chip 101. The mismatch is due to an influence of the inductance of the bonding wire 111. Accordingly, a standing wave is generated in response to the input signal, and the input signal is thereby attenuated.
In order to reduce the influence of the inductance of the bonding wire 111, the upper electrode 102 of the semiconductor chip 101 and the signal line 118a may be bonded with a shorter distance therebetween. However, a practical length of the bonding wire 111 cannot be short enough because of structural and manufacturing restrictions. Therefore, attenuation of the input signal attributable to generation of the standing wave cannot be avoided. Consequently, the input signal cannot excite the semiconductor chip 101 sufficiently, and it is difficult to obtain a desired detection output.
FIG. 2 shows one example of a voltage standing wave ratio (VSWR) with regard to a frequency of the input signal when observing the semiconductor chip 101 from the point C. Similarly, FIG. 3 shows a Smith chart which exemplifies a frequency locus of an input impedance when observing the semiconductor chip 101 from the point C.
In the case where a pin diode is substituted for the semiconductor chip 101 in the mounting structure in FIG. 1, a voltage standing wave is generated because of the existence of a similar impedance mismatch, and a signal is thereby attenuated.
It is desirable that the value of the VSWR may be in a target range close to 1, and no greater than 2. However, as shown in FIG. 2, the influence of the inductance of the bonding wire 111 increases the VSWR to exceed 2 along with an increase in the frequency over 25 GHz. Particularly, the value exceeds 3 in a millimeter-wave band at 30 GHz and above, whereby signal loss inside the circuit is increased and operation of the integrated circuit becomes impossible. Moreover, in the case when the VSWR is improved by adding an impedance matching circuit, the input impedance at the side of the semiconductor chip 101 as seen from point C has a high inductive impedance at 30 GHz and above as exemplified in FIG. 3. As a consequence, a matching method associated with parallel connection of capacitance components, which is frequently used in the microwave band, is not easily applicable and composition of such a matching circuit becomes difficult.
It is an object of the present invention to provide a microwave integrated circuit which can lower the VSWR inside the integrated circuit even in a quasi-millimeter-wave or millimeter-wave band.
A first aspect of the present invention inheres in a microwave integrated circuit and includes: a dielectric substrate having a signal line on a front surface of the dielectric substrate and a mount pad disposed adjacent to an end of the signal line in a longitudinal direction of the signal line; a semiconductor chip having an upper electrode and a lower electrode provided on opposite surfaces of the semiconductor chip, the lower electrode being mounted on the mount pad; a bonding block connecting a bottom surface of the bonding block to the end in the longitudinal direction of the signal line; and a wiring member configured to bond the upper electrode of the semiconductor chip and a top surface of the bonding block together.
A second aspect of the present invention inheres in a microwave integrated circuit and includes: a dielectric substrate having first and second signal lines on a front surface of the dielectric substrate, the first and second signal lines aligned on a longitudinal direction, and a mount pad disposed between facing ends of the first and second signal lines in the longitudinal direction; a semiconductor chip having a first electrode disposed on a bottom surface of the semiconductor chip and second and third electrodes disposed on a front surface of the semiconductor chip, the first electrode being mounted on the mount pad; bonding blocks connecting bottom surfaces of the bonding blocks to the respective facing ends of the first and second signal lines; and wiring members respectively configured to bond the second and third electrodes of the semiconductor chip and top surfaces of the bonding blocks together.